1. Field of the Invention
The present invention relates to an integrated circuit, and to a method of generating a layout of such an integrated circuit, and in particular to a technique for reducing the leakage current within such an integrated circuit.
2. Description of the Prior Art
In order to reduce dynamic power consumption within an integrated circuit, one technique employed is to turn off the clock signal to one or more components when those components are not required. By turning off the clock signal, no switching occurs within those components, and accordingly the dynamic power consumption is reduced.
However, power consumption can also arise due to leakage current, and accordingly even though the dynamic power can be reduced by turning off the clock to certain components, those components may provide leakage current paths which contribute to the overall power consumption, and hence the overall energy consumption, of the integrated circuit.
With the aim of reducing leakage current, it is known to employ power gating techniques to remove a power supply to certain circuit elements when they are not being used, so as to avoid them contributing to leakage current. Typically each of the circuit elements will be connected between two supply rails, one of the supply rails providing a power supply voltage level and the other supply rail providing a ground voltage level. In accordance with a known power gating technique, a gated supply rail is provided which is connected via power switches to one of the non-gated supply rails. Hence, by way of example, a gated VDD (power supply) rail can be provided by connecting that gated power supply rail to the non-gated VDD power rail via header switches. For any circuit elements that it is desired to power off during a power gated mode of operation, those circuit elements are connected between the gated VDD supply rail and the ground supply rail, rather than between the non-gated VDD supply rail and the ground supply rail. During a power gated mode of operation, the header switches are then turned off, causing the gated power supply rail to be disconnected from the non-gated power supply rail, thus removing the power from any circuit elements connected to that gated power supply rail.
As an alternative to gating the power supply rail, a gated ground supply rail can be created which is connected to the non-gated ground supply rail via footer switches. Circuit elements to be powered off in the power gating mode of operation are then connected between the non-gated VDD supply rail and the gated ground supply rail.
While such an approach can significantly reduce the leakage current, an issue that can arise is that the output from circuit elements that have been power gated can tend to float, i.e. the output voltage level transitions to a point between the logic one (VDD) and the logic zero (ground) level. Whilst this is not necessarily an issue if the output from a power gated circuit element is only received by other circuit elements that are also power gated, if an output from a power gated circuit element is provided as an input to another circuit element which is not power gated, then the floating nature of the output from the power gated circuit element can cause incorrect operation of the integrated circuit.
To address this issue, it is known to provide distribution networks to provide a predetermined static value as an input to any circuit structures containing a power gated circuit element whose output may be received by a non power gated circuit element, with that predetermined static value being chosen to ensure that the output from the power gated circuit element cannot adversely impact correct operation of the non power gated circuit element. In known systems, the circuit elements forming such distribution networks remain powered during the power gating mode of operation to ensure that the required predetermined static value is provided to the necessary power gated circuit elements.
An alternative power gating approach which has been the subject of significant academic research is referred to as zig-zag power gating. In accordance with the zig-zag mechanism, the above distribution networks are not required, since the zig-zag mechanism ensures that none of the gated circuit elements can have their output at a floating voltage level. Instead, a known sleep state is architected for the entire power-gated region of the integrated circuit which ensures that every circuit element to be power gated receives an input that will cause its output not to float. Every circuit element then has one of its supply rails provided by a gated supply rail that is turned off in the power gating mode of operation.
Two example papers which discuss zigzag power gating techniques are “Cell-Based Semicustom Design of Zigzag Power Gating Circuits” by Shin et al Proceedings of the Eighth International Symposium on Quality Electronic Design (ISQED '07) and “On leakage power optimization in clock tree networks for ASICs and general-purpose processors” by Homayoun el al, Sustainable Computing: Informatics and Systems 1 (2011), pages 75 to 87.
Whilst such zig-zag power gating techniques achieve significant reductions in leakage current, and avoid any power gated circuit elements having a floating output, they require both a gated power supply rail and a gated ground rail in addition to the non-gated power supply rail and non-gated ground rail, and in many production integrated circuits the power routing overhead of providing two such switched supplies cannot be afforded. In addition the zig-zag power gating approach requires a known sleep state to be architected for all of the circuit elements to be power gated. In practice, it can be very difficult to achieve such a known sleep state. For example, it is difficult for general purpose processors to have a known sleep state without very significant software effort.
For the above reasons, in many practical implementations it is not possible to implement zig-zag power gating, and instead the earlier-mentioned power gating approach is used, where a single gated supply rail is provided (either a gated VDD rail or a gated ground rail), and distribution networks of circuit elements are used where necessary to ensure that any gated circuit elements whose outputs could affect the correct operation of non-gated circuit elements during the power gated mode of operation have their outputs decoupled from the non-gated circuit elements or are forced to produce outputs that do not float when they are power gated.
However, as mentioned earlier, the circuit elements forming such distribution networks are powered during the power gated mode to ensure that the correct static value is provided to the necessary power gated circuit elements. As a result the circuit elements forming these distribution networks can contribute to leakage current during the power gated mode of operation. As process geometies shrink, the issue of leakage current is becoming more and more significant, and as a result the amount of leakage current resulting from such distribution networks is becoming a cause for concern. Accordingly, it would be desirable to provide a technique for reducing leakage current when such distribution networks are used in power gated modes of operation of the integrated circuit.